NetFPGA SUME: Toward 100 Gbps as research commodity

The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the research community. In order to make and validate timely and relevant research contributions, the wider research community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We present NetFPGA SUME, an FPGA-based PCIe board with I/O capabilities for 100Gb/s operation as NIC, multiport switch, firewall, or test/measurement environment. As a powerful new NetFPGA platform, SUME provides an accessible development environment that both reuses existing codebases and enables new designs.This work was jointly supported by EPSRC INTERNET Project EP/H040536/1, National Science Foundation under Grant No. CNS-0855268, and Defense Advanced Research Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under contract FA8750-11-C-0249.This is the author accepted manuscript. The final version is available from IEEE at http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6866035&sortType%3Dasc_p_Sequence%26filter%3DAND%28p_IS_Number%3A5210076%29

NetFPGA - Rapid prototyping of high bandwidth devices in open source

The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the wider community. In order to make and validate timely and relevant new contributions, the wider community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We demonstrate NetFPGA SUME, an open-source FPGA-based PCIe board for rapid prototyping of high bandwidth devices. NetFPGA SUME has I/O capabilities for 100Gbps operation as a networking device, computing unit, or for test and measurement.This work was jointly supported by EPSRC INTERNET Project EP/H040536/1, National Science Foundation under Grant No. CNS-0855268, and Defense Advanced Research Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under contract FA8750-11-C-0249. The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the National Science Foundation, Defense Advanced Research Projects Agency or the Department of Defense. The Xilinx XUP program has been a long-standing supporter of NetFPGA and the NetFPGA SUME project is only possible with their generous support. We thank the people at Digilent Inc. We thank Micron and Cypress Semiconductor for their generous part donations.This is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/FPL.2015.729396

NetFPGA: Rapid Prototyping of Networking Devices in Open Source

The demand-led growth of datacenter networks has meant that many constituent technologies are beyond the budget of the wider community. In order to make and validate timely and relevant new contributions, the wider community requires accessible evaluation, experimentation and demonstration environments with specification comparable to the subsystems of the most massive datacenter networks. We demonstrate NetFPGA, an open-source platform for rapid prototyping of networking devices with I/O capabilities up to 100Gbps. NetFPGA offers an integrated environment that enables networking research by users from a wide range of disciplines: from hardware-centric research to formal methods.This work was jointly supported by EPSRC INTERNET Project EP/H040536/1, National Science Foundation under Grant No. CNS-0855268, and Defense Advanced Research Projects Agency (DARPA) and Air Force Research Laboratory (AFRL), under contract FA8750-11-C-0249. The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the National Science Foundation, Defense Advanced Research Projects Agency or the Department of Defense.This is the accepted manuscript. The final version is available at http://dx.doi.org/10.1145/2785956.279002

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances

Network Function Virtualization (NFV) allows creating specialized network appliances out of general-purpose computing equipment (servers, storage, and switches). In this paper we present a PCIe DMA engine that allows boosting the performance of virtual network appliances by using FPGA accelerators. Two key technologies are demonstrated, SR-IOV and PCI Passthrough. Using these two technologies, a single FPGA board can accelerate several virtual software appliances. The final goal is, in an NFV scenario, to substitute conventional Ethernet NICs by networking FPGA boards (such as NetFPGA SUME). The advantage of this approach is that FPGAs can very efficiently implement many networking tasks, thus boosting the performance of virtual networking appliances. The SR-IOV capable PCIe DMA engine presented in this work, as well as its associated driver, are key elements in achieving this goal of using FPGA networking boards instead of conventional NICs. Both DMA engine and driver are open source, and target the Xilinx 7-Series and UltraScale PCIe Gen3 endpoint. The design has been tested on a NetFPGA SUME board, offering transfer rates reaching 50 Gb/s for bulk transmissions. By taking advantage of SR-IOV and PCI Passthrough technologies, our DMA engine provides transfers rate well above 40 Gb/s for data transmissions from the FPGA to a virtual machine. We have also identified the bottlenecks in the use of virtualized FPGA accelerators caused by reductions in the maximum read request size and maximum payload PCIe parameters. Finally, the DMA engine presented in this paper is a very compact design, using just 2% of a Xilinx Virtex-7 XC7VX690T device.This work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project PackTrack (TEC2012-33754) and by the European Union through the Integrated Project (IP) IDEALIST under grant agreement FP7- 317999. The stay of Sergio Lopez-Buedo at the University of Cambridge was funded by the Spanish Government under a ”Jose Castillejo” grant. Additionally, this research was sponsored by EU Horizon 2020 SSICLOPS (agreement No. 644866) research program and EPSRC through Networks as a Service (NaaS) (EP/K034723/1) project.This is the author accepted manuscript. The final version is available from IEEE at http://dx.doi.org/10.1109/ReConFig.2015.7393334

Low Power Optical Transceivers for Switched Interconnect Networks

The power-consumption of network equipment is under ever-increasing scrutiny. As part of an ensemble project seeking to reduce power-consumption within data-centers1, this work focuses on reducing the power consumption of photonic transceivers for future fast power gated and/or optical switching networks. Utilising an open-source toolkit, we show that Serializer/Deserializer (SERDES) dominates power consumption of traditional optical transceivers. This result has particular implications for the modulation format of future interconnects. At 25 Gb/s line rate, SERDES blocks of PAM-16 and 4-wavelength WDM are shown to have 53% and 79% lower power respectively compared with SERDES of serial NRZ as well as reduced power gating restoration time and energy

Power Optimized Transceivers for Future Switched Networks

Network equipment power consumption is under increased scrutiny. To understand and decompose transceiver power consumption, we have created a toolkit incorporating a library of transceiver circuits in 45-nm CMOS and MOS current mode logic (MCML) and characterize power consumption using representative network traffic traces with digital synthesis and SPICE tools. Our toolkit includes all the components required to construct a library of different transceivers: line coding, frame alignment, channel bonding, serialization and deserialization, clock–data recovery, and clock generation. For optical transceivers, we show that photonic components and front end drivers only consume a small fraction (<22%) of total serial transceiver power. This implies that major reductions in optical transceiver power can only be obtained by paying attention to the physical layer circuits such as clock recovery and serial–parallel conversions. We propose a burst-mode physical layer protocol suitable for optically switched links that retains the beneficial transmission characteristics of 8b/10b, but, even without power gating and voltage controlled oscillator power optimization, reduces the power consumption during idle periods by 29% compared with a conventional 8b/10b transceiver. We have made the toolkit available to the community at large in the hope of stimulating work in this field

Characterisation of Leukocytes in a Human Skin Blister Model of Acute Inflammation and Resolution

There is an increasing need to understand the leukocytes and soluble mediators that drive acute inflammation and bring about its resolution in humans. We therefore carried out an extensive characterisation of the cantharidin skin blister model in healthy male volunteers. A novel fluorescence staining protocol was designed and implemented, which facilitated the identification of cell populations by flow cytometry. We observed that at the onset phase, 24 h after blister formation, the predominant cells were CD16hi/CD66b+ PMNs followed by HLA-DR+/CD14+ monocytes/macrophages, CD11c+ and CD141+ dendritic cells as well as Siglec-8+ eosinophils. CD3+ T cells, CD19+ B cells and CD56+ NK cells were also present, but in comparatively fewer numbers. During resolution, 72 h following blister induction, numbers of PMNs declined whilst the numbers of monocyte/macrophages remain unchanged, though they upregulated expression of CD16 and CD163. In contrast, the overall numbers of dendritic cells and Siglec-8+ eosinophils increased. Post hoc analysis of these data revealed that of the inflammatory cytokines measured, TNF-α but not IL-1β or IL-8 correlated with increased PMN numbers at the onset. Volunteers with the greatest PMN infiltration at onset displayed the fastest clearance rates for these cells at resolution. Collectively, these data provide insight into the cells that occupy acute resolving blister in humans, the soluble mediators that may control their influx as well as the phenotype of mononuclear phagocytes that predominate the resolution phase. Further use of this model will improve our understanding of the evolution and resolution of inflammation in humans, how defects in these over-lapping pathways may contribute to the variability in disease longevity/chronicity, and lends itself to the screen of putative anti-inflammatory or pro-resolution therapies